There exists a continued effort to develop semiconductor memories having greater storage capacities and higher speed capabilities. Accordingly, recent efforts have been directed toward reducing the area required by each storage cell of the memory such that an integrated circuit chip can accommodate a greater number of such cells. Efforts are also directed toward the reduction of the various capacitances associated with the memory cells to enable high-speed electrical read and write operations thereof.
One approach taken to achieve a high density, high-speed dynamic random access memory (DRAM) is through the utilization of the trench technology. With this technique, the DRAM cell, comprising a pass transistor in series with a storage capacitor, is fabricated in a trench with the transistor formed over the capacitor. In this manner, the wafer area per cell is reduced, as the transistor need not be formed at a lateral location on the wafer with respect to the capacitor, as was heretofore a conventional technique. In order to optimize the performance of the trench DRAM cells, the storage capacitance was maintained as large as possible by extending the depth of the trench into the silicon wafer. While deeper trenches make possible larger storage capacitors, an inherent process limitation places a limit on the depth of the trench.
When etching a silicon wafer to form the noted trenches, certain process limitations cause such trenches to be tapered inwardly near the bottom of the trench. Hence, with narrow trenches, which are desirable in fabricating small area cells, the trench sidewalls would converge, or close together, at depths of only several microns below the wafer surface. Thus, efforts to form narrow trenches for further reducing the cell area requirements were counterproductive, in that the capacitance of the storage capacitor was correspondingly decreased, or at least limited.
The noted trench cells were accessed by bitlines diffused into the semiconductor material of the wafer. By utilizing bitlines of the noted construction, the junction capacitance thereof, with respective to the substrate, presented speed limitations for accessing the cells. Also, such cell structure was susceptible to soft errors, in the nature of incorrect electrical cell operation due to alpha particles entering the substrate.
From the foregoing, it can be seen that a need exists for an improved DRAM cell structure, and method of fabrication thereof, which provides a small cell area without compromising the storage capabilities of the storage capacitor. An additional need exists for a memory structure which exhibits reduced wordline capacitance, and a high immunity to alpha particle strikes. An associated need exists for a high density, high-speed DRAM array which can be fabricated by currently available silicon fabrication techniques.